Huawei's "Tau Scaling Law" Reshapes the Global Chip Supply Chain: From Process Pursuit to Systemic Breakthrough

Introduction

On May 25, 2026, at the IEEE International Symposium on Circuits and Systems (ISCAS) in Shanghai, He Tingbo, head of Huawei's semiconductor business, formally proposed the "Tau Scaling Law"—a strategy aimed at improving chip performance through system-level efficiency rather than transistor scaling alone. Its goal is to achieve transistor density comparable to 1.4nm-class advanced processes by 2031. The announcement came amid escalating U.S. export controls on advanced chip manufacturing equipment to China, leaving Huawei almost unable to obtain key facilities such as EUV lithography machines. Facing dual barriers—physical and political—Huawei chose a different path: instead of directly confronting TSMC, Samsung, and Intel in process scaling, it seeks to "assemble" performance equivalent to advanced processes from mature nodes by reshaping chip architecture and system integration.

This is not just a survival strategy for Huawei; it may also redefine how the semiconductor industry judges what is "advanced." This article will break down the event from four dimensions—technology impact, supply chain restructuring, competitive landscape, and regional strategy—and assess its implications for the global semiconductor industry over the next decade.

Background: Huawei under Blockade and Moore's Law Nearing Its End

Since being added to the U.S. Entity List in 2019, Huawei's chip supply chain has been increasingly tightened. Two rounds of export controls in October 2022 and October 2023 not only banned advanced chips and equipment but also restricted U.S. personnel from providing services to semiconductor companies in China. After 2025, further restrictions extended to mature tools for 16/14nm and below nodes, subjecting every stage of Huawei's design, manufacturing, and packaging to scrutiny over "U.S. technology content."

Meanwhile, the global semiconductor industry's own growth engine—Moore's Law—is slowing. TSMC's 3nm entered mass production at the end of 2022, 2nm is not expected to enter mass production until 2026, and the 1.4nm node has become an "ultimate threshold" that only a few players worldwide can touch. Each generation node costs over $5 billion in R&D, and cutting-edge manufacturing equipment such as High-NA EUV costs more than €300 million. The entire industry is searching for the next source of performance growth beyond mere scaling.

Huawei's Tau Scaling Law emerged precisely in this historical gap. At ISCAS, He Tingbo explicitly stated that physical transistor scaling is increasingly approaching its practical limits and that alternative paths must be found. She emphasized that future performance gains will come from reducing data movement, optimizing memory hierarchies, and lowering system latency. These seemingly software- and architecture-level improvements actually require deep innovation at the semiconductor hardware level to support them.

Deep Analysis

Technology Impact: The Three Pillars of Tau Scaling Law

Huawei's so-called "Tau Scaling Law" is not a specific process node, but a systematic methodology for performance growth. Based on disclosed information, its technical core can be summarized at three levels:

1. Dataflow Optimization: In the traditional von Neumann architecture, data movement consumes most of the energy and latency. The Tau Scaling Law emphasizes embedding computing logic into the dataflow to reduce dependence on high-cost memory access, thereby achieving higher effective throughput under the same transistor budget.

2. LogicFolding Architecture: This is a specific circuit-level innovation proposed by Huawei. By folding logic units in three dimensions and reusing space, it increases effective logic density per unit area without relying on lithographic scaling. The architecture is expected to be applied to future Kirin mobile processors and Ascend AI accelerators. From the statement, this is a design strategy of "exchanging architecture for density," using more interconnect layers and thermal management to compensate for the lack of physical transistor size.

3. Process-Packaging Synergy: Since front-end manufacturing processes cannot be broken through, Huawei must concentrate more functions into advanced packaging. This means that 2.5D/3D stacking, hybrid bonding, and chiplet technology will become the main competitive means for Huawei's chips.

Technical barriers remain enormous. He Tingbo admitted that "scaling still faces obstacles, including thermal management and new design tools." The power density generated by three-dimensional logic stacking may far exceed current thermal solutions; and the EDA tools needed to design such complex systems are currently basically monopolized by Synopsys, Cadence, and Siemens EDA. Huawei must establish new design flows or cooperate with other non-US EDA companies. This is not only a technical problem, but also a time problem—Huawei's given time window is 2031, which implies that it already has a relatively complete internal roadmap.In the equipment domain, advanced packaging only requires a subset of semiconductor manufacturing equipment, such as etchers, thin-film deposition tools, wafer bonders, and temporary carrier debonding systems. This provides Chinese equipment suppliers with an opportunity to narrow the gap with global leaders—because export controls on packaging equipment are generally less stringent than those on front-end lithography.

The greatest risk lies with traditional front-end equipment makers. Applied Materials, Lam Research, and KLA continue to face restrictions in the Chinese market, and if Huawei validates the feasibility of "mature process + advanced packaging," other companies worldwide may also reassess the rationality of overinvesting in expensive EUV lithography. Although ASML currently holds a monopoly, if system-level solutions gain traction, its customer base for High-NA EUV could shrink.

Competitive Landscape: The Contest Between Two Technical Paths

Huawei's long-term goal is to maintain global competitiveness in both mobile computing and AI computing. If the Tau Scaling Law succeeds, the global high-end chip market will form two models:

• Model A: Process Density Dominance (TSMC, Intel, Samsung route) — continuously pursuing smaller transistors, advancing toward 2nm, 1.4nm, and even smaller nodes. The advantage is that logic density has a physical benchmark, making heterogeneous integration easier to achieve.
• Model B: System Architecture Dominance (Huawei route) — leveraging mature process nodes as a foundation and achieving equivalent density through 3D architectures and packaging technologies. The advantages are circumventing equipment restrictions and achieving higher system efficiency, but engineering complexity and thermal management difficulty are enormous.

For NVIDIA and AMD, if Huawei's Ascend AI chips achieve competitive performance on specific inference workloads, they will create a substitution effect in both the Chinese market and third-world markets. This substitution will accelerate especially if the United States further restricts NVIDIA exports to China. For Qualcomm, a successful return of the Kirin processor would directly impact its share of China's high-end smartphone market.

It should be noted that Huawei's closed-loop ecosystem (self-developed chips + in-house equipment + HarmonyOS) provides a unique foundation for its system-level optimization. This "end-to-end" capability is something even fabless companies like Apple do not fully possess.

Regional Implications: A Global Supply Chain of "One Item, Two Chains" Begins to Take Shape- US: The U.S. Department of Commerce will inevitably keep a close watch on Huawei's progress in system-level technology, and future export controls may expand to heterogeneous integration equipment, advanced packaging materials, and even software algorithms. However, the marginal utility of such controls is diminishing, as China will accelerate the establishment of an alternative system. - Mainland China: Huawei has become the "pathfinder" for domestically produced advanced chips, and its supply chain partners (SMIC, JCET, Empyrean Technology, etc.) will form a de facto Chinese semiconductor ecosystem. The Chinese government may step up policy and financial support for this route. - Taiwan, China: Among TSMC's customers, the share from Mainland China has been declining year by year, but Taiwan's advantages in packaging and IP remain evident. If Huawei channels packaging orders to Mainland Chinese companies, it may accelerate the outflow of Taiwan's OSAT technology; however, TSMC's advanced packaging such as SoIC still leads. - South Korea and Japan: South Korea's Samsung and SK Hynix are constrained by the China-U.S. rivalry in memory and foundry sectors; Japan dominates in materials (photoresist, silicon wafers), but export restrictions put it in a dilemma—wanting to retain the Chinese market while not daring to defy U.S. bans. In the future, more "non-U.S. technology" hybrid operations may emerge. - Southeast Asia: Malaysia, Thailand, Singapore, and others are seen as neutral manufacturing bases. Huawei may diversify risk by establishing packaging and testing plants in the region, thereby elevating Southeast Asia's position in the chip supply chain.- Baseline scenario (50%): Huawei releases its first Ascend chip based on LogicFolding at the end of 2029, reaching the international 7nm/5nm level in inference performance, but still far from 1.4nm equivalence. The supply chain forms a pattern in which the "China dual-track" and "US-EU-Taiwan dual-track" run in parallel. - Optimistic scenario (30%): Huawei achieves 1.4nm equivalent density around 2031, and key EDA and manufacturing equipment complete localization. The global semiconductor industry chain truly splits into two sets of standards, driving the entire industry to rapidly migrate toward "system-level design." - Pessimistic scenario (20%): Due to further U.S. export controls, Huawei cannot obtain the required key technologies (such as HBM high-bandwidth memory), or internal R&D progress lags, making Tau Scaling Law more of a slogan. The global supply chain continues to maintain a US-dominated single system, but China's catch-up cost increases.

Industry Chain Analysis

Upstream: Equipment, Materials, EDA and IP

• Front-end lithography: Huawei still needs DUV lithography machines for mature process nodes, but this demand can be supplied by ASML's competitors Canon, Nikon, or China's SMEE; EUV is excluded, thereby reducing dependence on ASML.
• Etching and thin film: This is the most important incremental segment in mature processes and advanced packaging. Domestic equipment makers such as AMEC and NAURA have covered some of the processes.
• Materials: 3D stacking requires ultra-thin wafers, high-density dielectrics, and copper hybrid bonding materials. The related supply chain is still dominated by German, Japanese, and U.S. companies, and China has not yet fully replaced them.
• EDA: This is the biggest "bottleneck" Huawei faces, but domestic companies such as Empyrean and S2C are iterating rapidly, and Huawei's own toolchain is also being validated.

Midstream: Design, Manufacturing, Packaging

• Design: LogicFolding inevitably requires a highly customized physical design flow. Huawei will develop a methodology similar to a "chip compiler"—automated mapping from high-level language to physical layout. This will be the core asset of China's IC design over the next decade.
• Manufacturing: SMIC's 14nm/12nm capacity may be able to meet the needs of "mature process + system optimization." The yield and performance stability of its N+2 process will continue to improve with Huawei's push.
• Packaging: CoWoS and SoC foundations have been validated, but Huawei needs a more aggressive "logic-on-logic stacking" architecture, which places unprecedented demands on packaging precision and reliability. JCET, Tongfu Microelectronics, and ASE will all become key barriers.

Downstream: AI, Mobile Devices, and Automotive- AI: Ascend Accelerator will be the first choice for China's AI infrastructure in the inference market; if performance improves, it may challenge the demand for compliant alternatives to NVIDIA A100/H100. - Mobile devices: The return of the Kirin processor will reshape Huawei phones' high-end positioning and drive the domestic RF and power chip supply chains. - Automotive: Automotive chips have strict requirements for power consumption and reliability; Huawei's "system-level" strategy may also be applied to autonomous driving domain controllers.

Conclusion: An industry transformation from "process density" to "system intelligence"

The strategic significance of Huawei's "Tau Scaling Law" is no less than the emergence of "Moore's Law" in its time. It represents that the global semiconductor industry is shifting from being driven purely by process miniaturization to being driven by system-level architectural innovation. If Huawei ultimately succeeds, it will prove that "advanced" does not mean "smaller at 0.1nm," but rather "achieving the optimal balance of computing power, energy consumption, and cost under physical constraints."

This means: TSMC's monopoly is not unchallengeable; NVIDIA's GPU moat is not unbridgeable; and the U.S. export control system is not impenetrable.

The future of the global semiconductor supply chain will no longer be a single pyramid structure, but a coexistence of two or more parallel systems. In such a "dual-track era," both enterprises and nations must simultaneously master two technological logics, and choosing which path to take as a first mover will determine the geoeconomic landscape of the next decade.