Export Controls Reshape the Semiconductor Supply Chain: EDA, GAA, and Etching Equipment Become New Bottlenecks in 2026

From Equipment to Design: Semiconductor Supply Chain "Chokepoints" Are Proliferating Rapidly

Geopolitical tensions and trade restrictions are reshaping the foundational architecture of the semiconductor industry. Deloitte's latest TMT Predictions 2026 report points out that by 2026, key technologies in front-end and back-end chip manufacturing—such as precision etching, gate-all-around (GAA) transistors, and electronic design automation (EDA) tools—will become new supply chain bottlenecks. This means that beyond EUV lithography equipment, more "invisible" technology segments are being drawn into the range of export controls.

Deloitte further predicts that in 2026, at least US$30 billion will be spent globally on procuring critical technologies affected by trade barriers, covering EUV lithography equipment and co-packaging tools for high-bandwidth memory (HBM). Although substantial, this investment is equivalent to only about one-tenth of the approximately US$300 billion AI chip market. Yet it is precisely this narrow US$30 billion bottleneck that will determine whether the future US$300 billion in AI chips can be produced smoothly—a clear illustration of its strategic leverage value.

This article uses Deloitte's TMT predictions as a starting point to analyze how export controls are extending from equipment to EDA, GAA, etching materials, and other areas, and to assess their far-reaching impact on the entire semiconductor supply chain, corporate competitive dynamics, and the division of labor across countries/regions.

Export Control Lists Moving from "Hardware" to "Integrated Hardware–Software"

Over the past two years, the scope of U.S. export controls on semiconductors to China has expanded significantly. In 2024 and 2025, restrictions were first tightened and then partially relaxed, with a focus on EDA tools that support advanced AI accelerator design. In December 2024, Washington further expanded controls to cover software and tools that support the development and design of advanced computing nodes. GAAFET, an emerging transistor architecture for sub-5nm and sub-3nm logic design, was also explicitly brought within the scope of scrutiny.

These actions indicate that export controls are no longer limited to physical equipment itself, but have extended to transistor architectures, design methodologies, and software toolchains. The EDA flow—encompassing logic design, chip layout, simulation, AI-enhanced design, verification, and integration—is an indispensable step in developing advanced AI accelerators. If a region cannot obtain EDA tools and process design kits (PDKs) that support GAAFET design, it can only fall back to older transistor nodes or painstakingly develop proprietary EDA alternatives—both paths significantly lengthen product cycles and erode competitiveness.Furthermore, AI model weights — this “intangible asset” — have also begun to enter the export-control purview. The quality and scale of model weights have a direct bearing on the capabilities of AI-enhanced EDA tools. New compliance requirements are forcing companies to intensify scrutiny of end-uses, partners, and model transfer pathways. In 2026, EDA and logic design vendors may face more frequent inspections, as well as granular disclosure requirements covering foundry IP libraries, PDKs, and performance-test outputs. AI hardware co-design teams may also need to establish “trusted-country” pathways—for example, hosting model weights in secure IT facilities in the United States or its allies and allowing foundry partners to run verification tests only remotely. Such process re-engineering will significantly lengthen project timelines and raise costs for cross-border chip design projects.

Front-End Manufacturing: Beyond EUV, Etch and Materials Become the New Chokepoints

In wafer fabrication, EUV lithography has long been viewed as the most critical export-control tool. The United States has no domestic EUV production capability, but by cooperating with the Netherlands it has coordinated supplier shipments to maintain a strategic advantage. China, for its part, is trying to circumvent EUV restrictions through deep-ultraviolet (DUV) lithography tools customized by domestic equipment makers, combined with multi-patterning techniques. Deloitte notes that although these options are effective in the short term, they are far slower and more costly.

More subtly, precision etching equipment is now becoming the new focus. Advanced etching technology is essential for manufacturing cutting-edge AI chips at sub-5nm nodes. The industry uses double patterning, quadruple patterning, and spacer-based patterning to etch tiny features onto wafers. As a result, any etch process equipment originating from the United States—or designed and manufactured overseas using U.S. etch-related intellectual property—could be flagged as a new bottleneck in 2026.

Meanwhile, the lenses and mirrors in EUV optical systems, as well as the reticles/photomasks that carry the circuit-pattern blueprint, may also draw export-control attention. Specialty gases (such as silane and various fluorinated derivatives) and critical minerals (gallium, germanium, and antimony)—front-end manufacturing inputs—are also adding new friction points to the global chip supply chain.

Deloitte predicts that, in this environment, capacity ramp-ups at sub-5nm and sub-3nm nodes in the United States, Taiwan, and South Korea will continue to accelerate in 2026 and beyond. Mainland China, by contrast, is highly likely to remain focused on the mature DUV multi-patterning route. This means that global capacity for the most advanced process nodes will continue to tilt toward the United States and its allies, while China’s technological catch-up must still proceed amid multiple compounding costs.

Transmission Along the Industry Chain: A “Compliance Marathon” for Equipment, Foundry, and Design Firms## Industry Chain Transmission: The "Compliance Marathon" for Equipment, Foundry, and Design Companies

From upstream precision equipment and materials, to midstream foundry and packaging/testing, and downstream AI chip design, export controls are reshaping the "physical distance" of industry collaboration. AI system performance depends heavily on three mutually coupled technological links: advanced logic design, leading-edge front-end node manufacturing, and advanced packaging. Each link involves participants from different countries—IDMs, foundries, equipment suppliers, EDA and IP vendors, OSATs, system integrators, and government agencies.

In such a chain, imposing control barriers at any single link triggers a "ripple effect." For multinational equipment companies, being affected means capital expenditure plans must be re-evaluated on a regional basis. For equipment, component, and foundry suppliers, certification processes, upgrade procedures, and installation cycles will be longer than in 2024–2025. For chip design companies, "compliance" must be integrated as part of early-stage R&D rather than treated as a final legal review.

Competitive Landscape and Regional Divergence: Accelerating Bloc Formation

On one hand, export controls strengthen the bargaining power of established technology giants, such as the oligopolistic players in EUV and advanced etching equipment; on the other hand, they place non-U.S. allies in an awkward position—these countries both want to procure U.S. technology to secure their supply chains and must prove their own "trustworthiness."

Through a dual-pronged approach of export controls and the CHIPS Act, the United States aims to build a closed loop of domestic R&D and manufacturing. Taiwan and South Korea continue to serve as critical nodes thanks to their existing advantages in advanced process technology; Japan's materials and semiconductor equipment industry may absorb more supply chain shifts under "limited exemptions." Southeast Asia is gradually emerging as a new choice for packaging and testing, but tools required for advanced packaging, such as HBM co-packaging, remain subject to export licensing.

For mainland China, control pressure will force it to build a "de-Americanized" substitution system spanning EDA, materials, and manufacturing equipment. The vast domestic market for mature-node chips in automotive, industrial, and other sectors can provide demand support for substitute technologies, but at the very frontier of AI chips, the gap may widen further.

Investment Implications: The "Leverage Effect" of Bottleneck Links

There is a significant scale gap between the US$30 billion in controlled technology spending forecast by Deloitte and the US$300 billion AI chip market. This gap itself marks a turning point in investment logic: for the few companies that master critical technologies, market position and value are no longer determined solely by revenue scale, but rather by their "veto power" within the global supply chain.

For investors, close attention should be paid to changes in the compliance status of equipment makers and EDA suppliers, as well as regional companies with substitution capabilities amid export controls. At the same time, because certification and installation cycles are lengthening, companies with mature service networks and spare parts inventories will gain competitive advantages.In the long run, supply chain security will replace pure cost-effectiveness as the core metric for semiconductor capital expenditure. Within the next three years, control lists will continue to be dynamically adjusted, with coverage expanding from hardware lists to technology lists, materials lists, and even data model lists. In the next five years, two parallel semiconductor ecosystems may emerge: a leading-edge process ecosystem centered on the United States and its allies, and a mainstream process ecosystem led by China. The two will overlap in the mature process market, intensifying the risk of overcapacity. Over the next decade, if decoupling continues, the chip industry will face a decline in overall efficiency—but the resilience within each camp will strengthen.

Conclusion: The era of “technological sovereignty” in the semiconductor industry is arriving

Deloitte's forecast reveals an indisputable industry trend: technological leadership is no longer just a business issue but a national security issue. The entry of specialized terms such as EUV, EDA, GAA, and etching into export control documents means that the semiconductor industry has been brought into the core arena of great-power competition.

In the future, the competitiveness of companies along the industry chain will depend not only on process advancement or yield improvement, but also on their ability to “navigate” among multiple sets of control rules. For China's semiconductor industry, self-reliance and controllability have shifted from optional to mandatory; for the United States and its allies, ensuring that supply chains are controllable and trustworthy will become a long-term strategy. Whichever path is taken, the era of efficient division of labor in the global semiconductor industry is coming to an end, and an era of regionalization dominated by security is beginning.

At this point, understanding “where the next bottleneck lies” is more valuable than predicting “the next advanced process node.”