From 662.6 Billion to $1.59 Trillion: Restructuring of the Global Semiconductor Industry Chain Under the “Dual Track” of AI Computing Power and Mature Process Nodes

Key Takeaways

• In 2025, the global semiconductor market size was $662.6 billion, with a compound annual growth rate of 9.1% from 2026 to 2035, and is projected to reach about $1.5939 trillion by 2035; Asia-Pacific accounts for more than a 60% share, corresponding to about $397.6 billion in revenue.
• Value stratification is clear: logic chips account for 38.0% of the product mix, mature nodes at 28nm and above account for about 42.0% of the market, while advanced nodes at 7nm and below and "data centers and AI" are the fastest-growing segments.
• Foundry value is highly concentrated in advanced process nodes: at TSMC in 2024, 3nm accounted for 18% of wafer revenue, while advanced process nodes at 7nm and below accounted for 69% combined.
• The focus of technological competition is shifting from "single-process-node scaling" to system-level coordination across "process + advanced packaging + memory bandwidth + materials + intelligent manufacturing."
• The two main lines of regional division of labor—China's capacity expansion in mature process nodes, and the investments by the United States, Japan, and Europe in advanced process nodes, packaging, and materials—will simultaneously reshape the supply-demand balance and the geopolitical landscape.

Introduction

The market research firm market.us gives a set of ten-year forecasts in its semiconductor market report: in 2025, the global semiconductor market size was $662.6 billion, with a compound annual growth rate of 9.1% from 2026 to 2035, and by 2035 it will approach $1.5939 trillion. The report also cites the statistical scopes of the World Semiconductor Trade Statistics (WSTS) and the Semiconductor Industry Association (SIA), noting that global semiconductor sales had already approached $800 billion in 2025 and are expected to exceed $1 trillion in 2026.

There is an obvious gap between the two sets of figures, which itself is an entry point for understanding the current industry: different statistical scopes cover different ranges, and their boundaries should be noted when comparing them. But whichever statistical scope is used, the direction of the conclusion is the same—semiconductors are shifting from "consumer electronics cyclical products" to "underlying assets of compute infrastructure."

What is more worth analyzing is not the total volume, but the distribution of incremental growth. Growth is highly concentrated in AI-accelerated computing, high-bandwidth memory, advanced process nodes and advanced packaging, and power semiconductors supporting electrification; traditional large markets such as mature process nodes and consumer electronics play more of a ballast role.

This article does not repeat the report's figures; instead, it analyzes what this growth curve means for the global semiconductor industry from four dimensions: technology roadmap, supply chain transmission, competitive landscape, and regional division of labor.

I. Background: From the Consumer Electronics Cycle to the Compute Infrastructure Cycle

Over the past four decades, fluctuations in the semiconductor industry have mainly been driven by PC and mobile phone inventory and replacement cycles. The demand anchor of this round of expansion has shifted.Threefold support on the demand side. The first is AI servers and cloud infrastructure: SIA lists AI-related applications as a major demand driver of 2024 global semiconductor sales of $630.5 billion; NVIDIA reported fiscal 2025 data center revenue of $115.2 billion, up 142% year over year, with demand coming from accelerated computing platforms used for large language models and generative AI. The second is the end-device base: 2025 global smartphone shipments are close to 1.26 billion units, and IDC data shows global PC shipments of about 260 million units, with nearly 76 million units in a single quarter; in the report’s two dimensions of applications and end users, consumer electronics each account for a 28.0% share. The third is electrification and industrial automation: global EV sales are expected to exceed 20 million units, accounting for more than 25% of total vehicle sales; International Federation of Robotics data shows that in 2024 global new installations of industrial robots were about 542,000 units, with an operational stock of about 4.7 million units, and Asia accounted for nearly 75% of new installations. Every industrial robot and every electric drive system requires a large number of analog and power devices for sensing, voltage regulation, and motor control.

New physical constraints on the supply side. The International Energy Agency (IEA) estimates that by 2030 global data center electricity consumption will reach about 945 TWh, nearly double the current level. This means "compute per watt" will be as important as absolute performance, and energy efficiency is upgrading from an engineering metric to a procurement decision variable.

II. Technology Impact: The Layering and Synergy of Technology Roadmaps

1. Process technology shows a "dumbbell-shaped" structure. The report shows that mature nodes above 28nm account for about 42.0% of the market; their advantages lie in controllable costs, proven reliability, and long lifecycles, and they widely serve automotive electronics, industrial equipment, home appliances, and consumer products. At the same time, advanced nodes at 7nm and below are the fastest-growing segment, because they determine the upper limits of performance and energy efficiency for AI accelerators, high-end smartphone processors, and cloud CPUs. The industrial structure therefore appears strong at both ends and squeezed in the middle.

TSMC’s data confirms the concentration of value: in 2024, 3nm accounted for 18% of its wafer revenue, while 7nm and below advanced processes together accounted for 69%. Advanced processes are no longer a "technology showcase," but the main body of foundry revenue structure.

2. Advanced packaging becomes the second battlefield. IBM and Rapidus announced a collaboration focused on chiplet packaging manufacturing technology for 2nm-generation semiconductors, indicating that packaging has upgraded from a back-end process to a front-end-level technology race. A 2025 academic study shows that a thermal-aware chiplet layout method can reduce interconnect length by 11% and structural stress by 11%, while temperature rises by only 0.5%—such seemingly minor improvements are precisely the key to whether multi-chip systems can be mass-produced.3. Memory bandwidth becomes the antidote to the compute bottleneck. Micron reports that its HBM3E memory consumes about 30% less power than competing solutions while providing more than 1.2 TB/s of bandwidth for AI workloads. In AI training and inference, constraints on memory bandwidth and capacity often hit ceilings earlier than compute units do, which makes HBM one of the segments with the strongest bargaining power in the industry chain.

4. Environmental variables in lithography and materials. A peer-reviewed study in 2025 found that using EUV lithography at the 7nm node can reduce PFAS-containing layers by 18% compared with 7nm DUV immersion lithography. As major economies tighten regulation of per- and polyfluoroalkyl substances (PFAS), materials and process choices are gaining a compliance dimension, not just cost and yield dimensions.

5. Intelligence in manufacturing itself. A 2025 semiconductor manufacturing optimization study showed that AI-based capacity planning models can increase capacity by 1.8% and shorten manufacturing cycles by 1.8%. For capital-intensive fabs with manufacturing cycles lasting several months, improvements of this magnitude directly correspond to a capital efficiency difference on the order of hundreds of millions of dollars.

6. Power semiconductors tied to electrification. The U.S. Department of Energy notes that silicon carbide (SiC) semiconductors are key components in electric vehicle powertrains, used in inverters, onboard chargers (OBCs), and DC-DC converters. Compared with mature silicon-based solutions, SiC’s efficiency advantages in high-voltage and high-temperature scenarios make it one of the most technically demanding and capacity-constrained categories in automotive semiconductors.

Where are the technical barriers? First, the availability of EUV and more advanced lithography equipment; second, yield and thermal management engineering capabilities for advanced packaging; third, HBM stacking processes and power consumption control; fourth, EDA tools and the IP ecosystem; fifth, stable supply of materials such as high-purity silicon wafers, photoresists, and specialty gases. These five barriers are interdependent; a shortcoming in any single link will limit the output pace of the entire chain.

III. Industry Chain Analysis: Complete Transmission from Upstream to Midstream to Downstream

Upstream (equipment, materials, EDA/IP). It is the beneficiary with the highest certainty in this round of expansion, and also the most directly regulated target. With each generation of advanced process advancement, the consumption intensity of lithography, etching, thin-film deposition, metrology equipment, and high-purity materials continues to rise. At the same time, PFAS regulation, rare gas supply, and silicon wafer capacity pose potential cost and compliance risks.Midstream (design, manufacturing, packaging and testing). On the design side, the division of labor is further refined: logic chips account for 38.0% of the product mix, while analog semiconductors are the fastest-growing device category, because they connect digital systems with real-world signals such as temperature, pressure, sound, motion, and voltage, and are widely used in batteries, chargers, inverters, and motor drives. On the manufacturing side, the core tension is that capex is concentrating in advanced nodes while mature-node capacity (especially 28nm and above) continues to expand. On the packaging and testing side, value is rising due to chiplets and 2.5D/3D integration.

Downstream (cloud service providers, OEMs, automakers, telecom and industrial customers). Demand from cloud and data center customers is shifting from “buying chips” to “buying rack-level compute,” and the focus of bargaining is shifting toward system integration and energy-efficiency metrics; automotive and industrial customers are more focused on long-term supply assurance and automotive-grade certification than on the most advanced nodes.

IV. Supply Chain Impact: Who Benefits, Who Is Under Pressure

Beneficiaries:

• Advanced-node foundries and their equipment and materials suppliers: the trend of revenue structure being dominated by advanced nodes (7nm and below account for 69% of TSMC’s wafer revenue) is still strengthening.
• HBM and high-end memory suppliers: inelastic bandwidth demand from AI workloads directly translates power consumption and bandwidth metrics into pricing power.
• Advanced packaging and testing service providers: chiplet standardization and R&D investment in 2nm-generation packaging push packaging to the center of value distribution.
• SiC and analog device suppliers: long-term demand from electrification and industrial automation gives them relatively strong counter-cyclical characteristics.
• Manufacturing intelligence solution providers: throughput improvements and cycle-time compression from AI capacity planning have direct economic value for wafer fabs.

Parties Under Pressure:

• Foundries and design companies with high product homogeneity in mature nodes: concentrated capacity release may create price competition pressure.
• System and module manufacturers dependent on capacity in a single region: supply uncertainty from export controls and geopolitical policies has not yet been eliminated.
• General-purpose computing solutions lacking an energy-efficiency advantage: under data center power constraints, performance per watt will directly influence procurement decisions.

V. Competitive Landscape: How the Competitive Landscape Is Changing

Compute side: NVIDIA’s revenue scale in AI accelerated computing (FY2025 data center revenue of $115.2 billion, +142% YoY) illustrates the extremely high concentration of this market. However, continued investment by cloud providers in in-house accelerators means that over the long term this share structure may still be diluted, especially as inference workloads account for a rising share.Foundry side: The mismatch between value and capacity is the main tension. Advanced process nodes are concentrated in the hands of a few manufacturers, while mature nodes are rapidly expanding capacity in China—industry estimates show that China's 28nm and above capacity may approach one third of the global total by 2025, with monthly capacity exceeding 10 million wafers, mainly serving automotive, home appliances, power systems, and industrial control equipment. This means the global foundry market is forming a two-tier structure of "advanced-node oligopoly + mature-node multipolarity."

Packaging side: IBM's collaboration with Rapidus on chiplet packaging manufacturing technology for the 2nm generation represents a new competitive path—not directly catching up in the most advanced logic processes, but competing for standards and process influence in the relatively open arena of advanced packaging.

Analog and power side: As the fastest-growing device category, competition in analog semiconductors relies more on product portfolio, customer qualification, and long-term supply capability than on process leadership, leaving room for regional players.

VI. Regional Implications: Changes in the Positions of Countries and Regions in the Industry Chain

• United States: Maintains strength in EDA, IP, semiconductor equipment, AI accelerator chips, and cloud computing power, while influencing the flow of technology in global supply chains through export controls. Its industrial policy focuses on partially reshoring advanced manufacturing.
• Taiwan, China: A global hub for advanced-node foundry and advanced packaging. TSMC's revenue mix shows that advanced nodes are already the core of its operations, keeping it continuously in the spotlight in geopolitical issues.
• South Korea: Its strong position in memory, especially HBM, makes it one of the hardest links to replace in the AI computing supply chain.
• Japan: Has deep accumulated strengths in materials and equipment, and through Rapidus's collaboration with IBM, is attempting to rebuild a domestic manufacturing presence in the 2nm generation and advanced packaging.
• Europe: Holds a key position in lithography equipment, materials, and automotive semiconductors, and is also one of the main formulators of regulatory rules for materials such as PFAS; the spillover effects of its regulation deserve attention.
• Mainland China: Has formed scale advantages in mature nodes, analog and power semiconductors, and EV and industrial domestic-demand markets; the pace of its capacity expansion is a key variable affecting global mature-node prices.
• Southeast Asia: Continues to serve as a capacity destination for packaging/testing and electronics assembly, benefiting from supply chain diversification.

VII. Investment Perspective: Why the Capital Markets Are Watching

The capital markets' focus on semiconductors has shifted from "cyclical elasticity" to "structural capital expenditure." Three rationales support this shift:

First, demand visibility is improving. Data center electricity consumption is projected to approach 945 TWh by 2030, providing a relatively predictable physical anchor for investment in computing infrastructure. Second, value distribution is concentrating in a few segments—advanced nodes, HBM, and advanced packaging. What these three have in common is high technical barriers, long capacity-expansion cycles, and strong pricing power. Third, manufacturing efficiency itself is becoming part of investment returns; the 1.8% throughput improvement and 1.8% cycle-time reduction brought by AI capacity planning have an amplifying effect given the high fixed-asset base of wafer fabs.

The risks are equally clear: the industry cycle has not disappeared, and the concentrated release of mature-node capacity may suppress prices; export controls and materials regulation may alter cost structures; changes in the pace of AI capital expenditure will be directly reflected in orders for advanced nodes and HBM.

VIII. Long-Term Outlook: 3 Years, 5 Years, 10 Years

Next 3 years: Incremental growth will still be dominated by AI training and inference, HBM iteration, 2nm-generation volume production, and advanced packaging capacity expansion. AI adoption in manufacturing (capacity planning, yield optimization) is moving from pilot projects to routine deployment. Mature nodes are entering a capacity digestion period, and price competition is intensifying.

Next 5 years: Chiplets are expected to develop clearer design and packaging standards, thereby changing the boundaries of the division of labor between chip design and foundry; automotive semiconductors, driven by SiC and analog devices, will become the second-largest growth pole; combined with data center power constraints, energy-efficiency metrics will move to the core of product specifications. At this stage, the total market is expected to continue advancing toward the trillion-dollar scale.

Next 10 years: At a 9.1% CAGR, the market size will be approximately $1.5939 trillion in 2035, and Asia-Pacific will remain the largest regional market. The real variable is not the total but the structure—if value concentration in advanced nodes and advanced packaging continues to rise, bargaining power across the industrial chain will further converge toward a few segments and a few regions, while competition in mature nodes and analog devices will become more regionalized and localized.

IX. Conclusion

First, this round of growth is uneven. Along the path from $662.6 billion to $1.5939 trillion, the vast majority of the increase comes from AI compute, HBM, advanced nodes, and advanced packaging, rather than broad-based growth across all semiconductor categories.

Second, the main battlefield of competition is shifting. From “whose process is more advanced” to “who can combine process, packaging, memory bandwidth, materials, and manufacturing efficiency into a system that can be mass-produced and delivered.” IBM and Rapidus’s collaboration on 2nm-generation chiplet packaging, as well as research advances such as thermal-aware chiplet layouts, are evidence of this shift.

Third, the industry’s geopolitical structure is taking on a two-tier form: advanced nodes are highly concentrated in a few regions, while mature nodes tend toward multipolar distribution. The risk of the former is concentration; the risk of the latter is overcapacity. Understanding this is more important than remembering any single market-size figure.