Advanced packaging enters a new battlefield: Analysis of the rise of CoPoS technology and the competitive landscape of the global semiconductor industry

In the AI chip race, advanced packaging has become a key variable determining computing power supply. In July 2026, at WAIC 2026, Enflame Technology and Shanghai Xianfang Technology jointly released China's first CoPoS advanced packaging sample for AI computing chips, marking the first deep integration of domestic high-end AI chips with domestic CoPoS packaging technology. Meanwhile, TSMC disclosed at its investor conference a complete roadmap for CoPoS from pilot production to mass production: trial production in 2027, and mass production in the second half of 2028. From CoWoS to CoPoS, the difference is just one word, yet it may represent a structural leap in the semiconductor packaging industry.

This article will analyze why CoPoS is becoming the new battleground in advanced semiconductor packaging from dimensions such as technology roadmap, industry chain impact, competitive landscape, and regional layout.

The Bottleneck of CoWoS: The Deep Driving Force Behind Technology Iteration

CoWoS is the benchmark solution for 2.5D advanced packaging. It uses a silicon interposer to achieve high-density interconnection between GPU/CPU dies and HBM high-bandwidth memory, and packages them on an ultra-large substrate. This solution solved the integration challenges of AI chips, but it has gradually exposed three major pain points:

• High cost: The silicon interposer is expensive, accounting for more than half of the total packaging cost.
• Limited size: Limited by 12-inch wafers, the supported chip area has an upper limit. For example, NVIDIA's B200 chip area exceeds 800 mm²; cutting square chips from a circular wafer results in a material utilization rate of less than 70%.
• Warpage risk: The coefficient of thermal expansion (CTE) severely mismatches between silicon chips (CTE about 2.7 ppm/°C) and organic substrates (CTE about 16 ppm/°C), making large-size packages prone to warping, affecting yield.

As AI model Token call volume soars (from January to July 2026, global weekly Token calls for AI models increased from 6.4 trillion to 46.7 trillion), ultra-large AI chips have an increasingly urgent need for packaging that offers "larger area, higher interconnection, and lower cost." When chip packaging area jumps from 3.3x reticle size to more than 9x, traditional wafer-level solutions can no longer meet demand, and CoPoS has emerged at the right moment.

Technology Leap: How CoPoS Solves CoWoS's Pain Points

CoPoS (Chip-on-Panel-on-Substrate) is a new panel-level advanced packaging technology. Its core difference lies in replacing the circular silicon wafer originally used as the interposer with a square panel. In the CoWoS approach, chips are first placed on a circular silicon interposer and then packaged onto the substrate as a whole; CoPoS first places chips on a square panel, completes RDL (redistribution layer) interconnection, and then packages onto the final substrate.

This architecture brings four core advantages: First, significant improvement in area utilization. The effective area utilization rate of a 12-inch circular wafer is about 70%, while a square panel can reach over 95%. Taking a 510×515mm panel as an example, its effective area is about 4.5 times that of a 12-inch wafer, and the packaging cost per unit area is expected to be reduced by 20% to 30%.

Second, the upper limit of package size is significantly raised. CoWoS currently supports a maximum package size of about 5.5 times the mask area, while CoPoS can support more than 9.5 times, providing ample room for multi-HBM stacking and chiplet integration in next-generation AI chips.

Third, capacity bottlenecks are expected to be fundamentally broken through. Panel-level packaging not only yields multiple times more output per panel than a wafer, but also can reuse or retrofit large-generation production lines from the display panel industry, offering a new path for rapid capacity expansion.

Fourth, natural compatibility with glass substrates. The long-term evolution direction of CoPoS is glass core substrates. Glass offers low warpage, high dimensional stability, excellent electrical insulation, and finer wiring precision, with interconnect density expected to reach 10 times that of organic substrates, delivering better thermal dissipation and signal integrity for high-computing-power chips.

An industry insider used a pizza analogy: CoWoS is like cutting rectangular pieces from a round pizza, where there is always leftover crust at the edges; CoPoS is like spreading the pizza on a square baking tray, with almost no waste, greatly increasing output per unit area.

TSMC's roadmap: a clear path from validation to mass production

As the absolute dominant player in advanced packaging, TSMC has the most systematic and in-depth CoPoS deployment. According to public information, TSMC has set up a CoPoS trial production line, entered the joint equipment and process validation stage, and is advancing square panel solutions in three specifications: 310×310mm, 515×515mm, and 750×620mm. 2026 is a key validation period, 2027 for trial production, and mass production in the second half of 2028.

In terms of capacity planning, TSMC's Taiwan fab is expected to achieve small-scale mass production in 2028, with monthly capacity of no less than 500 panels; by the end of 2029, monthly capacity will increase to 12,000 panels; in 2030, it will grow 241% year-over-year to 30,000 panels; in 2031, it will grow another 177% to 53,000 panels. The Chiayi AP7 plant has been designated as the core mass-production base, scheduled for completion in June 2026, with large-scale capacity release from the end of 2028 to 2029. TSMC's Arizona advanced packaging plant in the United States will also be equipped with CoPoS production lines, expected to be introduced in 2029-2030. TSMC also stated that even with mass production in 2028, it will take another 2-3 years to form sufficient supply scale; the full CoPoS process integrating glass core substrates is scheduled for mass production after 2030.On the customer side, NVIDIA is expected to become CoPoS's first customer. Its next-generation Feynman series GPUs have been included in the CoPoS adaptation plan: the first-generation products are expected to adopt 3D stacking and SiC carrier heat dissipation solutions in 2028; the Feynman Ultra version, launching in 2029, will fully adopt CoPoS, using the larger package area to accommodate more GPU chiplets and memory. In addition, HPC chips from AMD, Broadcom, and Google are also undergoing technical integration in parallel, and existing CoWoS customers will switch to CoPoS in phases.

The equipment supply chain has already swung into action. According to media reports, the first batch of CoPoS equipment test prototypes has arrived at TSMC subsidiary VisEra. Equipment makers such as Canon, DISCO, Applied Materials, and Lam Research have all secured their positions and entered the validation stage. TSMC has also imposed strict confidentiality controls on the CoPoS supply chain, requiring local equipment and material partners in Taiwan to restrict information sharing; some technologies are expected to be used exclusively by TSMC for several years after volume production begins.

Industry Chain Analysis: Impact on the Entire Industry Chain

The rise of CoPoS is not just a technological upgrade in the packaging segment, but a reshaping of the entire semiconductor industry chain.

Upstream: Equipment and Materials

On the equipment side, panel-level packaging requires new lithography tools, electroplating equipment, die bonders, and temporary bonding and debonding equipment. Existing equipment in the display panel industry can be retrofitted and reused, creating opportunities for suppliers with panel equipment expertise such as Canon. Meanwhile, DISCO's dicing equipment and Applied Materials' and Lam Research's deposition and etching tools also need to adapt to square-panel processing.

On the materials side, glass substrates are the core variable. Glass suppliers, glass through-via processing, RDL materials, and carrier substrate materials will all see new demand. Organic substrate manufacturers need to cope with substitution pressure, but TSMC has revealed that it is cooperating with substrate suppliers, suggesting that organic substrates will remain a transitional solution for some time to come.

Midstream: Packaging and Manufacturing

Through its coordinated CoWoS and CoPoS layout, TSMC has further consolidated its dominance in advanced packaging. The CoPoS capacity plan shows that advanced packaging is being upgraded from an "auxiliary process" to a "strategic high ground." For OSAT players such as ASE and Amkor, the technical barriers and capital expenditures of CoPoS are extremely high, which may widen the gap with TSMC, but may also prompt them to seek differentiation opportunities in the panel-level packaging niche.

Downstream: AI Chip DesignCoPoS's larger packaging area and higher interconnect density lift the limitations that AI chips face in size and performance. Major manufacturers such as NVIDIA, AMD, Broadcom, and Google will be able to design more complex multi-Chiplet architectures, integrate more HBM stacks, and drive the continued upgrading of AI computing power. At the same time, CoPoS's cost advantages also help reduce the packaging cost of AI chips, positively impacting AI server prices and cloud service capital expenditures.

Regional Implications: Shifts in Regional Industry Positions

Taiwan, China: The Chiayi AP7 fab will become CoPoS's first mass-production base, giving Taiwan, China a first-mover advantage in panel-level packaging technology validation, equipment supply chains, and talent. TSMC's confidentiality controls also help keep the core technology on the island.

China: Enflame Technology and Shanghai Xianfang jointly released CoPoS samples, marking a critical step forward for mainland China in the advanced packaging field. Although there is still a gap with international advanced levels in mass-production maturity and equipment supply chains, panel-level packaging provides mainland China with a possible path to bypass the limits of traditional wafer-level packaging. Local supporting industries such as glass substrates and packaging equipment will also benefit from the domestic substitution trend.

United States: TSMC's Arizona fab plans to introduce CoPoS capacity, meaning the United States is making substantial progress in the advanced packaging field. Combined with the CHIPS Act's subsidies for domestic packaging, the United States is expected to build a certain scale of CoPoS capacity by 2029-2030, reducing its dependence on Asian packaging capacity.

Japan and Europe: Although no CoPoS deployment is directly mentioned, Japan's technological accumulation in semiconductor materials and equipment makes it a key player in the CoPoS supply chain (e.g., Canon, DISCO). Europe may participate through the equipment and materials segments.

Investment Perspective: Capital Expenditures and Market Opportunities

CoPoS opens a new growth curve for semiconductor capital expenditures. According to TSMC's capacity plans, from 2028 to 2031, CoPoS monthly capacity will grow more than 100-fold (from 500 wafers to 53,000 wafers), meaning that demand for panel-level packaging equipment, materials, and testing services will grow exponentially. Equipment makers Applied Materials, Lam Research, Canon, DISCO, and potential glass substrate suppliers will all become direct beneficiaries.Investors need to watch three key signals: first, the verification progress of TSMC's CoPoS pilot production line; second, the mass-production adoption milestone of NVIDIA's Feynman series; third, the pace of maturity of mainland China's CoPoS supply chain. Risks also need attention. Analyst Ming-Chi Kuo has cautioned that the substrate and equipment manufacturers currently participating in CoPoS verification may not be the ultimate winners, because the technology roadmap may still iterate, and some segments may be exclusively integrated by TSMC. In addition, panel-level packaging imposes extremely high demands on yield, warpage control, and inspection equipment, which may cause mass production to fall short of expectations.

Long-Term Outlook: Industry Landscape for the Next Three to Ten Years

Short term (2026-2027): CoWoS remains the absolute mainstream, while CoPoS is in the verification and trial-production stage. TSMC's pilot production line will determine the final parameters for equipment and processes, and NVIDIA's adaptation plans will drive the supply chain to take shape.

Medium term (2028-2030): CoPoS enters the mass-production ramp-up phase. TSMC's Taiwan fab and Arizona fab release capacity one after another, NVIDIA's Feynman series fully adopts CoPoS, and customers such as AMD and Broadcom gradually switch over. Glass substrates begin to be introduced, but the complete glass-core-substrate CoPoS process is not expected to mature until after 2030.

Long term (2030-2035): CoPoS is expected to become the mainstream packaging solution for AI computing chips. Panel-level packaging may integrate with technologies such as 3D stacking and optical interconnect, pushing packaging from a "back-end process" toward the "front-end core." Different technology roadmaps in regions such as China, the United States, and Japan may form a multipolar competitive landscape. Whether TSMC can maintain its monopoly depends on its technology iteration speed and supply-chain integration capabilities, while whether mainland Chinese manufacturers can achieve differentiated breakthroughs depends on the maturity of domestically produced equipment and materials.

Conclusion

The rise of CoPoS marks the upgrade of semiconductor packaging from a "supporting process" to a "strategic high ground." Its technical significance lies in resolving the fundamental limitations of CoWoS in area, cost, and warpage control, opening new physical space for the continued evolution of AI chips. At the industry competition level, TSMC, with its first-mover advantages, capacity planning, and customer lock-in, is highly likely to extend its dominant position in advanced packaging; however, the technical barriers of panel-level packaging also provide a window of opportunity for other players. For the semiconductor supply chain, CoPoS will give rise to a new growth cycle for equipment, materials, and substrates, and reshape the regional division of labor within the industry. Over the next five years, the intensity of competition in advanced packaging will be no less than that in wafer manufacturing, and CoPoS is precisely the focal point of this new battle.