Study on Self-Heating and Radiation Hardness of 3nm GAA-FET SRAM: Profound Impact on Advanced Process Reliability

3nm GAA-FET SRAM Self-Heating and Radiation Hardness Study: Far-Reaching Impact on Advanced Process Reliability

What Happened?

In July 2026, researchers from San Jose State University (SJSU) and Sandia National Laboratories jointly published a technical paper systematically evaluating the self-heating effect and radiation hardness of SRAM based on 3nm GAA-FET (Gate-All-Around Field-Effect Transistor). The paper proposed a novel Channel Bottom Dielectric Isolation (Channel-BDI, C-BDI) technology, comparing it with conventional Source/Drain Bottom Dielectric Isolation (SD-BDI) and Punch-Through Stopper (PTS) structures. Results showed that the C-BDI structure significantly improved radiation hardness while maintaining source/drain-to-substrate connections, and all tested structures were completely immune to alpha-particle-induced Single Event Upsets (SEU).

Why Is This Important?

GAA-FET is the next-generation transistor architecture after FinFET and has been adopted by leading foundries such as Samsung, TSMC, and Intel for 3nm and below processes. As the core unit of cache and on-chip memory, SRAM's reliability and radiation hardness directly determine the stability and lifespan of processors in key applications such as data centers, aerospace, and military. Self-heating was already a concern in the FinFET era, but with GAA-FET's nanowire/nanosheet structure having narrower heat conduction paths, the self-heating problem is more severe and can cause performance degradation, threshold voltage shift, and even device failure. Moreover, as AI accelerators and high-performance computing (HPC) chips demand increasing SRAM capacity, radiation-induced soft errors (e.g., single event upsets) become more sensitive in advanced processes due to reduced node capacitance. This study not only provides crucial TCAD simulation references for reliability design of GAA-FET SRAM but also has far-reaching implications for the entire semiconductor industry chain.

Background

#### Company Background

• San Jose State University: Located in the heart of Silicon Valley, it has long-term expertise in semiconductor device physics and TCAD simulation, maintaining close collaboration with industry (e.g., Intel, Applied Materials).
• Sandia National Laboratories: A national laboratory under the U.S. Department of Energy, long engaged in radiation hardness research for nuclear weapons systems and aerospace electronics. Its research results are often incorporated into design specifications for U.S. defense and space-grade chips.

#### Technical BackgroundGAA-FET achieves better electrostatic control and lower leakage current by completely wrapping the gate around the nanosheet or nanowire channel, making it the mainstream choice for 3nm and below process nodes. However, because the channel is surrounded by the gate and dielectric layers, heat dissipation paths are severely restricted, leading to an exacerbated self-heating effect. At the same time, as one of the most densely packed circuit structures, the shrinking area of SRAM cells makes it easier for a single particle strike to cause multiple cell upsets (MCU).

• Traditional radiation hardening methods include adding bottom dielectric isolation (BDI) between the substrate and source/drain, but BDI cuts off heat dissipation paths, worsening self-heating. The C-BDI proposed in the paper places the dielectric layer under the channel rather than under the source/drain, maintaining a thermal conduction path from source/drain to substrate while improving radiation hardness, offering a new approach to balancing thermal management and radiation-hardened design.Involved technical routes:
• GAA-FET (3nm node): This study directly targets 3nm GAA-FET SRAM, and its self-heating and radiation hardness characteristics will affect the adaptability of this node in fields such as aerospace, defense, and automotive.
• Bottom Dielectric Isolation (BDI): BDI technology was originally introduced to reduce leakage current and improve short-channel effects, but this study shows it significantly enhances resistance to radiation-induced soft errors.
• Novel C-BDI: By moving the isolation layer from below the source/drain to below the channel, it provides radiation protection while maintaining a thermal conduction path, potentially becoming the mainstream solution for radiation-hardened design of future GAA-FET SRAM.
• SRAM bit-cell circuit: The single-event upset cross-section of 6T SRAM increases with process scaling. This study verifies that the BDI structure is completely immune to α-particle SEU, which is of great significance for designing high-reliability SRAM for atmospheric neutron environments.

• Technical barriers:
• C-BDI process integration difficulty: Precisely depositing a thin dielectric layer below the nanosheet channel without damaging the channel lattice imposes extremely high requirements on atomic layer deposition (ALD) and selective etching.
• Trade-off between self-heating and radiation hardness: Traditional SD-BDI offers good radiation resistance but increases thermal resistance; C-BDI requires multiple iterative optimizations between device-level thermal simulation and radiation simulation. Currently, it is only based on TCAD and needs tape-out verification.
• Metrology and detection: It is necessary to develop nanoscale thermal imaging technology for local temperatures at the 3nm scale, as well as heavy ion/proton irradiation testing capabilities for evaluating single-event effects.

#### Supply Chain ImpactAffected segments in the supply chain: 1. EDA and TCAD tool vendors: Such as Synopsys, Cadence, Siemens EDA. The TCAD simulations used in this study (paper from SJSU, possibly based on Synopsys Sentaurus or Silvaco) need to update self-heating and radiation models to support the C-BDI structure. Foundries and IP companies need to synchronize calibration. 2. Equipment suppliers: - Deposition equipment: ALD equipment for the ultra-thin dielectric layers (such as SiN or SiO₂) required by C-BDI, with suppliers including ASM International, Lam Research, Applied Materials. - Etching equipment: Requires high-selectivity etching to remove the sacrificial layer beneath the source/drain regions while retaining the dielectric below the channel. Lam, Tokyo Electron, AMEC, etc. may benefit. 3. Material suppliers: - High-k dielectrics and work function metals: HfO₂, TiN, etc. for GAA-FETs, with suppliers including Entegris, Merck, JSR. - Isolation materials: The selection of dielectric materials for C-BDI needs to balance thermal conductivity and dielectric constant, and new material requirements may emerge. 4. Wafer foundries: - TSMC: Its 3nm N3 series already uses FinFET, but 2nm N2 will transition to GAA-FET. The results of this study may prompt TSMC to consider the C-BDI option in its N2 SRAM solution. - Samsung: Its 3nm GAA-FET process is already in mass production. If it wants to enter the high-reliability market, it needs to evaluate radiation hardness requirements. The introduction of C-BDI will increase process complexity, but may differentiate its aerospace/defense foundry business. - Intel: Its 20A (2nm) and 18A (1.8nm) both adopt GAA-FET RibbonFET. Intel Foundry Services (IFS) may leverage this technology to attract government orders. 5. IP and design services: IP companies providing SRAM compilers, memory compilers, and radiation-hardened libraries (such as ARM, Synopsys, SST) need to update their GAA-FET SRAM IP to incorporate self-heating and radiation models.

• Who benefits?
• EDA vendors with mature TCAD radiation models and self-heating models.
• Equipment suppliers capable of providing C-BDI integration processes.
• Foundries that prioritize mass production of GAA-FET radiation-hardened SRAM (e.g., Samsung Foundry may thus secure U.S. defense orders).Who is at risk?
• Manufacturers relying on traditional FinFET radiation-hardened SRAM (e.g., GlobalFoundries, UMC) may lose aerospace/defense market share.
• IP companies that fail to update GAA-FET radiation models in time may be excluded from high-end supplier lists.

#### Competitive Landscape

• How will the competitive landscape change?
• Foundry level: Samsung has started mass production on 3nm GAA-FET, but its radiation hardness performance has not yet been disclosed. TSMC and Intel need to demonstrate the radiation reliability of their GAA-FET SRAM at the 2nm/1.8nm nodes. Whichever obtains certification from Sandia or similar institutions first will dominate the high-reliability advanced process foundry market.
• EDA level: Synopsys and Cadence need to deeply integrate self-heating and radiation simulation capabilities into their design flows. Ansys' Solido chip sign-off tool, which can interface with TCAD, may gain an early advantage.
• IDM level: Chip design companies like AMD and NVIDIA that rely on TSMC/Samsung foundry services use large amounts of SRAM in their AI accelerators (e.g., NVIDIA H100's 80MB L2 cache). Self-heating issues causing performance throttling or reduced lifespan will directly impact product competitiveness. If foundries cannot provide reliable GAA-FET SRAM, they may turn to chiplet/advanced packaging to replace some monolithic SRAM with SRAM from mature processes.

• How might market shares adjust?
• The aerospace and defense semiconductor market is currently dominated by mature processes (e.g., 65nm, 45nm), but there is a clear trend toward migrating to sub-7nm processes. Manufacturers offering high-reliability GAA-FET foundry services (e.g., Samsung in collaboration with Sandia) are expected to gain significant share between 2027-2029, estimated to rise from the current ~10% to 30%.
• Traditional radiation-hardened foundries (e.g., BAE Systems, Cobham) will be marginalized if they cannot acquire advanced process capabilities.

• #### Regional Implications- United States: The alliance between Sandia National Laboratories and American companies (such as Intel and Micron) will strengthen its leadership in radiation-hardened advanced process nodes. The defense industrial base (DIB) may drive the construction of domestic GAA-FET production lines, reducing reliance on Asian foundries.
• Taiwan, China: As the global foundry leader, TSMC must keep pace with GAA-FET radiation reliability research. If TSMC introduces a C-BDI option at 2nm, it can solidify its aerospace orders (e.g., from SpaceX, NASA), but due to export controls, it cannot provide such radiation-hardened processes to China.
• South Korea: Through collaboration with the Agency for Defense Development (ADD), Samsung Electronics may leverage this research to strengthen its 3nm GAA-FET position in the high-reliability market and pursue Trusted Foundry certification from the U.S. Department of Defense.
• Mainland China: SMIC and Hua Hong are still at the FinFET stage, with GAA-FET mass production plans delayed. Research on self-heating and radiation hardness provides technical direction for catching up, but given constraints in EDA and equipment, commercialization in the short term is not feasible. China focuses on radiation-hardened SRAM at mature nodes (e.g., 65nm, 40nm), but the performance gap is widening.
• Japan: Rapidus, in collaboration with imec to develop 2nm GAA-FET, can reference this study to optimize its SRAM reliability and attract automotive and industrial customers.
• Europe: imec has deep experience in nanosheet devices and TCAD; the results of this study will be integrated into imec's industry consortium projects, helping equipment vendors like ASML and KLA develop related metrology solutions.

#### Investment Perspective

• Short-term catalysts: Foundries announcing that GAA-FET SRAM has passed Sandia radiation certification (may lead to stock price increases for related equipment and material suppliers).
• Long-term value: If C-BDI technology is adopted by mainstream processes, it will generate sustained revenue for suppliers of advanced ALD equipment (e.g., ASM International) and ultra-thin dielectric materials. Additionally, license fees for EDA vendors' radiation simulation modules targeting 3nm are expected to grow.
• Risk factors: The C-BDI process is costly and may only be used in high-reliability products, while the mass market will still focus on self-heating optimization. If self-heating issues are not effectively mitigated, they will limit GAA-FET applications in HPC, prompting AI chip makers to shift toward chiplet solutions.

• #### Long-Term Outlook- Within 3 years (2026-2029): Samsung and TSMC will introduce varying degrees of BDI technology in their 3nm/2nm processes to improve SRAM radiation hardness. Self-heating effects will be mitigated by new materials (such as diamond substrates or graphene heat dissipation layers), but not completely resolved.
• 5 years (2030): Radiation hardness of GAA-FET SRAM becomes a standard requirement for high-reliability chips, with C-BDI or similar structures becoming mainstream. Integrated self-heating and radiation co-simulation in the EDA workflow becomes standard.
• 10 years (2036): With the rise of CFET (Complementary FET) or 3D stacked SRAM, thermal management and radiation protection face new challenges. The current research results of C-BDI will serve as a foundation, inherited or improved by next-generation devices.

Conclusion

The most important industry judgment of this study is: In the post-graphene GAA-FET era, reliability design has expanded from simple performance-power-area (PPA) to joint thermal-radiation management, which will become a key barrier for foundries to enter the aerospace, defense, and high-end automotive markets. Although C-BDI technology is still in the TCAD stage, it reveals a direction: through clever physical isolation and thermal path design, radiation resistance can be enhanced without sacrificing heat dissipation. For the industry chain, this study reminds each link—EDA, materials, equipment, and foundry—that they must evolve synergistically; otherwise, even with the highest transistor density, the reliability requirements of critical infrastructure cannot be met.

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• Sources:
• Original technical paper: Lu et al., "Self-Heating and Radiation Hardness Studies of 3nm GAA-FET-Based SRAM with Different Substrate Isolation Techniques," arXiv, July 2026. https://doi.org/10.48550/arXiv.2607.05789
• Semiconductor Engineering report: https://semiengineering.com/3nm-gaa-fet-sram-review-evaluates-self-heating-and-radiation-hardness-sjsu-sandia/